About Me
I am a teaching assistant professor and researcher in computer architecture in the ECE department at University of Illinois Urbana-Champaign. I am currently leading efforts to develop novel models and frameworks for microarchitecture optimization. I am also involved in the development of courses in VLSI design and hardware verification.
Research Interests
- Computer Architecture: CPU and accelerator microarchitectures; generalizing hardware acceleration.
- AI/ML for Systems and Architecture: ML for microarchitecture search and optimization.
- Models of Computing: Non-conventional models of computing, emerging technologies.
Recent Teaching
- Spring 2026: ECE 425 - Introduction to VLSI System Design
& ECE 391 - Computer Systems Engineering - Fall 2025: ECE 427 - Advanced VLSI System Design
& ECE 391 - Computer Systems Engineering - Summer 2025: ECE 391 - Computer Systems Engineering
- Spring 2025: ECE 411 - Computer Organization and Design
& ECE 425 - Introduction to VLSI System Design - Fall 2024: ECE 498HK - Advanced VLSI System Design
& ECE 391 - Computer Systems Engineering
Education
University of Illinois at Urbana-Champaign
2020 – 2023Ph.D. Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
2018 – 2020M.S. Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
2014 – 2017B.S. Computer Engineering
Work Experience
Teaching Assistant Professor, UIUC
Aug 2023 – PresentCourses developed: ECE 427/498HK (Advanced VLSI System Design).
Courses taught: ECE 391, 411, 425, 427.
Hardware Engineer, Startup
Mar 2026 – PresentMicroarchitecture modeling and optimization.
Research Intern, AMD
May 2022 – Aug 2022Designed and evaluated PIM-based methods of improving memory latency for CPUs equipped with HBM.
Research Intern, Google
May 2021 – Aug 2021Developed microarchitectures for RISC-V vector processors.
Research Intern, IBM
May 2018 – Aug 2018Worked on near-memory acceleration using the IBM ConTutto FPGA platform.
Publications
Tandem Processor: Grappling with Emerging Operators in Neural Networks
ASPLOS 2024 (Link)
Soroush Ghodrati, Sean Kinzer, Hanyang Xu, Yoonsung Kim, Byung Hoon Ahn, Rohan Mahapatra,
Dong Kai Wang, Lavanya Karthikeyan, Amir Yazdanbakhsh, Jongse Park, Nam Sung Kim, Hadi Esmaeilzadeh.
MESA: Microarchitecture Extensions for Spatial Architecture Generation
ISCA 2023 (Link)
Dong Kai Wang, Jiaqi Lou, Naiyin Jin, Edwin Mascarenhas, Rohan Mahapatra, Sean Kinzer, Soroush Ghodrati, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Nam Sung Kim.
DiAG: A Dataflow-inspired Architecture for General-purpose Processors
ASPLOS 2021 (Link)
Dong Kai Wang, Nam Sung Kim.
A²M: Approximate Algebraic Memory Using Polynomial Rings
ISLPED 2019 (Link)
Dong Kai Wang, Nam Sung Kim.
AxMemo: Hardware-Compiler Co-Design for Approximate Code Memoization
ISCA 2019 (Link)
Zhenhong Liu, Amir Yazdanbakhsh, Dong Kai Wang, Hadi Esmaeilzadeh, Nam Sung Kim.
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network
MICRO 2018 [Best Paper Nominee] (Link)
Mohammad Alian, Seung Won Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang,
Thomas Roewer, Adam McPadden, Oliver O'Halloran, Deming Chen, Jinjun Xiong, Daehoon Kim,
Wen-mei Hwu, Nam Sung Kim.
Projects / Services / Honors
Ongoing Projects
Exploring Microarchitecture for Future High-Performance RISC-V CPUs (Collaboration)
RISC-V SoC with MESA-Guided CGRA Acceleration (Collaboration)
Professional Services
- Reviewer: Integration, the VLSI Journal (2024) | IEEE Transactions on Computers (2023)
- Treasurer: IEEE CEDA Central Illinois Chapter (2023-2025)
Patents
- US20240211393 - Leveraging Processing in Memory Registers as Victim Buffers
- US18/663713 - (Pending) Dynamic Translation and Optimization For Spatial Acceleration Architectures
- US18/301776 - (Pending) Dataflow-Based General-Purpose Processor Architectures
Honors
AMD HACC Outstanding Researcher Award 2024